Design and implementation of FPGA recursive architecture based on Steger algorithm

ZHANG Yuan; ZHANG Guang-jun; JIANG Jie

doi:10.13873/j.1000-97872008.09.017

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Design and implementation of FPGA recursive architecture based on Steger algorithm

更新时间：2025-09-11

- Design and implementation of FPGA recursive architecture based on Steger algorithm
- Issue 9, Pages: 78-81(2008)
- 作者机构：
  
  北京航空航天大学仪器科学与光电工程学院精密光机电一体化技术教育部重点实验室
- 作者简介：
- 基金信息：
- DOI：10.13873/j.1000-97872008.09.017
  CLC： TP29-AI
- Published：2008
- 稿件说明：
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[1]张远,张广军,江洁.Steger算法的FPGA递归逻辑结构设计与实现[J].传感器与微系统,2008(09):78-81.

ZHANG Yuan, ZHANG Guang-jun, JIANG Jie. Design and implementation of FPGA recursive architecture based on Steger algorithm[J]. 2008, (9): 78-81.
[1]张远,张广军,江洁.Steger算法的FPGA递归逻辑结构设计与实现[J].传感器与微系统,2008(09):78-81. DOI： 10.13873/j.1000-97872008.09.017.

ZHANG Yuan, ZHANG Guang-jun, JIANG Jie. Design and implementation of FPGA recursive architecture based on Steger algorithm[J]. 2008, (9): 78-81. DOI： 10.13873/j.1000-97872008.09.017.

摘要

提出了一种以Steger算法为基础

基于现场可编程逻辑门阵列（FPGA）的递归流水逻辑结构

采用递归逻辑结构避免大规模高斯模板卷积带来的运算复杂度

同时

逻辑结构不受不同高斯参数选择的影响

增强了实用性

利用FPGA并行性完成多路运算

实现光条纹中心点提取。该逻辑结构更适用于连续图像数据的实时处理。

Abstract

A FPGA pipelined recursive logical architecture is put forward based on Steger algorithm

which adopts recursive logical architecture to avoid operation complexity generated by large-scale Gauss template convolution.This logical architecture can not be influenced by different Gauss parameter

and practicability can be enhanced

Multiple arithmetic and light stripe center detect are realized by parallelism of FPGA.This logical structure can be applied to process real-time sequential image.

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references

基于EZ U SB与FX2的通用数据传输模块设计 [J]. 陈茜,刘文怡,熊继军,张文栋. 微计算机信息 . 2006(35)

一种条纹中心线快速亚像素提取方法 [J]. 胡坤,周富强. 光电技术应用 . 2005(06)

机器视觉[M]. 科学出版社 , 张广军编著, 2005

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