2nd-order Σ-Δ modulation micro-accelerometer based on digital circuit

LI Yang; LI Xiao-lin; WU Jian; ZHOU Xiao-feng; CHE Lu-feng

doi:10.13873/J.1000-9787(2015)01-0091-03

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2nd-order Σ-Δ modulation micro-accelerometer based on digital circuit

更新时间：2025-09-11

- 2nd-order Σ-Δ modulation micro-accelerometer based on digital circuit
- Vol. 34, Issue 1, Pages: 91-93(2015)
- 作者机构：
  
  1. 中国科学院上海微系统与信息技术研究所传感技术联合国家重点实验室
  2. 中国科学院大学
- 作者简介：
- 基金信息：
- DOI：10.13873/J.1000-9787(2015)01-0091-03
  CLC： TN79
- Published：2015
- 稿件说明：
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[1]李洋,黎晓林,吴健,周晓峰,车录锋.基于数字电路的二阶Σ-Δ调制微加速度计[J].传感器与微系统,2015,34(01):91-93.

LI Yang, LI Xiao-lin, WU Jian, et al. 2nd-order Σ-Δ modulation micro-accelerometer based on digital circuit[J]. 2015, 34(1): 91-93.
[1]李洋,黎晓林,吴健,周晓峰,车录锋.基于数字电路的二阶Σ-Δ调制微加速度计[J].传感器与微系统,2015,34(01):91-93. DOI： 10.13873/J.1000-9787(2015)01-0091-03.

LI Yang, LI Xiao-lin, WU Jian, et al. 2nd-order Σ-Δ modulation micro-accelerometer based on digital circuit[J]. 2015, 34(1): 91-93. DOI： 10.13873/J.1000-9787(2015)01-0091-03.

摘要

为了简化模拟电路部分的设计

减少模拟电路的干扰

提出了一种基于数字电路的Σ-Δ调制微加速度计。在传统由纯模拟电路搭建的Σ-Δ接口电路基础上

将基于运算放大器的比例放大、微分、积分电路使用现场可编程门阵列（FPGA）进行实现。使用分立元件搭建了PCB板级电路

实现了采样频率为50 k Hz的二阶Σ-Δ闭环调制接口电路。测试结果表明:该加速度计灵敏度为1.4 V/gn

系统基带内闭环噪声密度小于400μgn/Hz1/2。

Abstract

In order to simplify design of analog circuit and reduce interference of anolog circuit

a Σ-Δ modulation micro-accelerometer based on digital circuit is presented. Field programmable gate array（ FPGA） is used to implement the PID circuit based on structure of traditional Σ-Δ interface circuit designed with pure analog circuit.PCB circuit is designed and a 2nd-order Σ-Δ closed-loop interface with its sample frequency 50 k Hz is built. Test results show that sensitivity of accelerometer is 1. 4 V / gn

and the closed-loop noise density is less than 400 μgn/Hz1 /2.

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references

一种圆片级硅三层键合的三明治加速度传感器 [J]. 徐玮鹤,林友玲,车录锋,李玉芳,熊斌,王跃林. 传感技术学报 . 2008(02)

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