In order to adapt to increase of the image compression processing in current sensor networks

presents a low storage discrete wavelet transform（DWT） VLSI architecture.Around us scattered all kinds of image acquisition devices

including monitor

computer

mobile video cameras

and growing demand for image precision is higher and higher

which make traditional image compression software processing speed gradually unable to meet the people’s needs

so it is necessary to consider using hardware processing to accelerate.Wavelet transform is often used for image compression

while the use of 5/3 lifting wavelet technology to implement hardware is relatively easy.In order to reduce on chip storage of hardware

through special scheduling operations mode to carry out parallel computing of row and column to effectively reduce on-chip storage demand.After RTL-level simulation and synthesized by SMIC 0.18 μm process

the results show that the scheduling method saves cache unit significantly

and with 100 MHz clock

it ensures fast processing on high-definition（HD） images

and meets needs of image compression decoding in current sensor network.