A novel process to fabricate capacitive accelerometers integrated with Au/Si galvanic cell protection and antifuse on SoI wafer is presented and realized.The process employs the device layer of SoI wafers to shape the beam and the surface electrode

while micromachining the handle layer to form the mass plate.The release hole is formed by DRIE etching from the front side

and then to release the mass plate by TMAH etching

meanwhile

the beam and the surface electrode are protected by Au/Si galvanic cell.Being off-state before TMAH etching

the antifuse is broken through to on-state after TMAH etching.The silicon is passivated when the area ratio of gold and silicon is more than 5∶1 by measuring the polarization curv

e of gold and silicon in 60 ℃ 25 %TMAH.The capacitive accelerometer structure is successfully fabricated

the range of unreleased and released beam width is 9.4

1

0 μm which indicates that the Au/Si galvanic cell protection is realized.Two breakdown antifuses in parallel have 5

2

5 kΩ on-state resistance.