A novel generic architecture of smart cascaded chip based on technology of system on chip（ SoC） is presented. This structure can be connected to different sensors and allows chip adopting cascade to expand the storage capacity of the system. Master-slave control mode is used

the operations of all cascade chips’memory are controlled and switched automatically by master chip through the interconnection between two pins of cascadechip. This mode of extended memory has fewer lines between different chips

higher reliability and lower power consumption compared with traditional method. The chip is designed and realized by CMOS technology with a line width 0. 18μm and 12 bit analog to digital converter （ ADC） is integrated

control module

512 k × 12 bit static random access memory（ SRAM） and interface. Experimental results show the system composed of cascaded chips has the advantage of small in size

stable characteristics

flexibility. It has already applied in pressure and acceleration measurement.