A high cost-effective VLSI implementation of advanced encryption standard（AES） algorithm is proposed.In order to reduce hardware resource

reversible hardware designs of two core parts（ByteSub and MixColumn）are presented with the technology of module reuse.In order to enhance the speed of encryption/decryption

the pipeline technology is introduced for outer and inner of the round operation.The architecture of round key expansion is designed to solve the problem of round key synchronous distribution at high-speed encrypting/decrypting.The experiment results show that this design not only correctly implement high-speed encryption/ decryption of AES

but also has higher cost effective compared with other current designs.