A low power consumption compressed sensing circuit for electrocardiogram（ ECG） signals is designed based on compressed sensing（ CS） theory. Making use of the periodicity of ECG signals

the bits of accumulator is determined by precalculating and compressed processing the maximum value of data in advance

avoid using redundant registers in the circuit

thus the power consumption is reduced effectively and data compression ratio is improved. Reconstruction verification is carried out by using the Bayesian learning algorithm. Verification results show that the logic gate number of CS circuit decreases from 42 071 gates to 25 029 ones and the power consumption is lowered from 11. 247 μW to 6. 847 μW

achieving a power reduction of 39. 12 %. The percentage of root-mean-squared error of reconstructed signals reaches 1. 14 %.