Using the configurable advantages of the devices of the field programmable gate array（ FPGA）

the convolutional neural network is implemented on the FPGA

the trained network parameters are stored in the memory of the chip of the FPGA in layers and blocks

and an independent computing array is configured for each layer of the network. Using high-level synthesis tools and C + + as design language

adjust and optimize the design of hardware structure. Finally

CIFAR 10 dataset is used to verify the design of the new structure

which improves the efficiency of image classification of the original structure by 31 %

and reduces the occupancy of hardware resources.