To improve the battery life of biological electrical signal detection system

a low power consumption type successive approximation analog-to-digital converter（ SAR ADC） is designed

in order to reduce the power consumption of the SAR ADC

a new kind of digital to analog converter（ DAC） switch strategy is proposed. It reduces the power consumption of the DAC part

and also implements the DAC output common mode level stable

so the simplest dynamic latch comparator can meet the requirements. SAR ADC is designed and simulated under the UMC 80 nm CMOS process. The simulation results show that under the condition of 1 V power supply voltage and 200 k Hz sampling frequency

the power consumption is only 525 n W

the effective bit is 9. 96

and the quality factor FOM value is 2. 6 f J/conversion-step.