Timing error detection and correction（ EDAC） techniques can effectively eliminate timing margin in digital circuit design. To solve the problem of large area and performance overhead brought by traditional EDAC circuit

an energy efficiency timing error tolerant register with in-situ correction（ error in-situ correction flip-flop

ESCFF） is proposed. Based on the traditional register

14 transistors are added

by detecting the difference between the internal nodes of the main latch and input end signal to get the timing error information

and the in-situ realtime error correction is completed by timing borrowing. Based on SMIC 40 nm process

the error tolerant circuit is applied to the domestic self-designed commercial processor CK802. The simulation results show that compared with the reference design without error tolerant function

the energy consumption is saved by 47. 5 % and performance is improved by 16. 7 % at voltage of 0. 6 V. Compared with the EDAC techniques based on Razor-Lite

the area is reduced by 4. 5 % and energy efficiency is improved by 10. 6 %.