Taking the independently developed micro-machined silicon resonant accelerometer（ MSRA） as research object

a bandwidth test scheme based on phase locked loop（ PLL） demodulation circuit is designed for the bandwidth test of its drive circuit. Firstly

SIMULINK simulation model is established for the phase transfer function of the PLL driving circuit

and the closed-loop model is analyzed. It can be concluded that the excitation signal generated by field programmable gate array（ FPGA） is loaded on the input port of the PLL

which is equivalent to the input signal of the PLL under the change of external acceleration frequency

and the output amplitude of the driver circuit of the accelerometer is read out by the demodulation circuit based on the PLL. This bandwidth test model is consistent with the actual test situation of MSRA. Experimental results show that the measured bandwidth of + 3 d B of MSRA PLL driver circuit is 210 Hz

which is basically the same as the 216 Hz obtained by the model simulation. This test method has the characteristics of high precision

easy implementation and low cost

and can meet the bandwidth test requirements of the PLL driving circuit.