In order to increase chip integration

3D stacking is used. The vertical interconnection of chips is achieved

through through silicon vias（ TSV）

it can effectively increase the integration degree. Bonding is used to realize 3D integrated interconnection. The structural interconnection and electrical interconnection of the chip are realized. Reliability can be effectively analyzed and the design cost is reduced by using the computer simulation and simulation bonding process. Bonding process of the double-layer chip simulation is carried out by COMSOL software

and the reliability is analyzed at the working temperature. The intermediate layer is BCB for two chips with diameter of 14 μm TSV. Bonding simulation of cyclobutene is carried out. Simulation results show that the maximum shear force that the two-layer chip can withstand is 20 MPa

and the tensile force is 0. 45 N

which is consistent with common welding results. Simulation results can simulate the reliability of the bonding interface to some extent. On this basis

simulate the reliability of bonding areas under different pitches

different pad sizes and different solder materials

and observe the Von mesis stress and find that the soldering reliability is best when the pad distance is 25 μm; tin eutectic soldering is more reliable than copper-copper direct soldering when the pad radius is large.