For the speed of rail defect detection requirements

a type of on-line defect inspection algorithm and system implementation based on field programmable gate array（ FPGA） is presented for rail flaw detection. An experimental system is set up

functions including electromagnetic inductance signal pre-processing

acquisition

defect characteristics extraction and network data transmission. Among these

excitation signal synthesis

signal demodulation algorithm

ADC and DAC timing control and defect characteristics extraction are realized by using FPGA. Timing control interface chip and defect feature extraction algorithms can realize simultaneously with pipeline and multi-channel parallel design method of FPGA. This design can improve the calculation efficiency and real-time performance compared with single processor structure. Rail defect detection experiments verify the correctness defect extraction algorithm. System performance analysis shows that the system has good application prospect in high speed scenarios.