A 2. 4 GHz two-stage fully differential power amplifier based on 65 nm complementary metal-oxidesemiconductor（ CMOS） technology is designed. The power amplifier uses on-chip transformer to realize the conversion between single-end signals and differential signals and impedance matching of input and output and uses the analog predistortion technology that takes the drive stage as predistorter to enhance linearity

so as to achieve high gain

high integration and high linearity chip of power amplifier. The chip area is 1. 08 mm ×1. 37 mm. Simulation result shows that the power amplifier achieves the-1 d B output power of 22. 9 d Bm

the power add efficiency of 23. 5 %

the small signal gain of 27. 2 d B

and the third-order inter-modulation distortion of-35. 6 d Bc at the operating frequency of 2. 4 GHz.