Paper defect image processing algorithm based on FPGA hardware implementation is simple in structure

can not meet needs of complex image algorithms

aiming at this problem

propose a hardware software collaborative real-time paper defect image processing system based on FPGA. The system uses FPGA chip as core of the system

CCD camera capture images

DDR2 SDRAM as external memory to cache image data

SOPC as control core

so hardware software can coordinate joint paper defect image processing

image processing module which is easy for hardware implementation compiled with Verilog HDL

to realize corresponding image processing function; function which is difficult to be achieved by hardware module referred to CPU in SOPC to achieve.Experiments show that the real-time property of system is strong

which can satisfy speed requirement of paper defect image processing

and can carry out complicated image algorithm operation

at the same time

it has characteristics of simple design and low cost.