LI Yang, LI Xiao-lin, WU Jian, et al. 2nd-order Σ-Δ modulation micro-accelerometer based on digital circuit[J]. 2015, 34(1): 91-93. DOI: 10.13873/J.1000-9787(2015)01-0091-03.
实现了采样频率为50 k Hz的二阶Σ-Δ闭环调制接口电路。测试结果表明:该加速度计灵敏度为1.4 V/gn
系统基带内闭环噪声密度小于400μgn/Hz1/2。
Abstract
In order to simplify design of analog circuit and reduce interference of anolog circuit
a Σ-Δ modulation micro-accelerometer based on digital circuit is presented. Field programmable gate array( FPGA) is used to implement the PID circuit based on structure of traditional Σ-Δ interface circuit designed with pure analog circuit.PCB circuit is designed and a 2nd-order Σ-Δ closed-loop interface with its sample frequency 50 k Hz is built. Test results show that sensitivity of accelerometer is 1. 4 V / gn
and the closed-loop noise density is less than 400 μgn/Hz1 /2.